1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory elements and a nonvolatile semiconductor memory device including the nonvolatile semiconductor memory elements.
2. Related Art
In a conventional nonvolatile semiconductor memory element, the potentials of the control gate electrode and the source/drain regions are controlled, so that charge injection into or charge release from the charge accumulating layer provided between the channel region and the control gate electrode is caused. In this manner, the charge amount in the charge accumulating layer is adjusted, so as to switch the threshold voltages of the element (or the control gate voltages to be switched between an ON state (a conductive state) and an OFF state (a nonconductive state) of the region between the source and drain of the element). Thus, information writing is performed.
In nonvolatile semiconductor memory elements of the above described type, the threshold voltage is switched between two values, so as to store 1-bit information in one element. Therefore, to achieve higher integration, more than 1-bit information needs to be stored in each memory element. As a method of storing more than 1-bit information in each one element, there has been a known method by which more than two different threshold voltages are obtained through fine adjustment of the charge amount in each charge accumulating layer (see Masayuki Ichige, et al., “A novel self-aligned shallow trench isolation cell for 90 nm 4-Gbit NAND Flash EEPROMs”, in Technical Digest of 2003 Symposium on VLSI Technology, pp. 89-90, and Osama Khouri, et al. “Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories”, in Analog Integrated Circuits and Signal Processing, vol. 34 (2003), pp. 119-131, for example).
By the method of obtaining two threshold voltages through fine adjustment of the charge amount in the charge accumulating layer, it is necessary to restrict a variation (hereinafter denoted by “ΔVTH”) of each threshold voltage to a sufficiently small value. The reason for this requirement is as follows. The element described here is an n-type element. When 2-bit information is stored in each one element, it is necessary to adjust the threshold voltages in four ways. The lowest threshold voltage has a negative value, and the highest threshold voltage has a value higher than the power supply voltage (hereinafter denoted by “VDD”). Meanwhile, there need to be two different threshold voltages between zero and the power supply voltage. Therefore, it is necessary to satisfy the relationship, VDD>2×ΔVTH. Here, a specific value of ΔVTH in a case where a verifying function is not provided is reportedly about 2.3 V (see Masayuki Ichige, et al. “A novel self-aligned shallow trench isolation cell for 90 nm 4-Gbit NAND Flash EEPROMs”, in Technical Digest of 2003 Symposium on VLSI Technology, pp. 89-90). A specific value of ΔVTH in a case where a verifying function is provided is reportedly about 0.5 V (see Osama Khouri, et al. “Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories”, in Analog Integrated Circuits and Signal Processing, vol. 34 (2003), pp. 119-131). Therefore, even in a case where a verifying function is provided, it is impossible to set VDD at a lower value than approximately 0.5V×2=1V. This fact has greatly hindered the achievement of a low power supply voltage required to reduce power consumption.